Using DDR3 RAM on Zynq with Vivado + VHDL

$8-15 USD / hour

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nesten 8 år siden

$8-15 USD / hour

Simple Vivado project demonstrating the use of AXI DMA. The project must include a Vivado workflow with custom editable VHDL code that will use an AXI master to read/write directly to DDR ram from PL. In addition the PS must be able to read what is written from PL using the same shared DDR RAM.

Electrical Engineering

Prosjekt-ID: 10569266

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Aktiv 8 år siden

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5 frilansere byr i gjennomsnitt $13 USD/time for denne jobben

@ahmedmohamed85

Dear sir I have more than 9 years experience in digital design and I am a professional vivado designer in addition I already have Zedboard please check my profile also please message me so that we can discuss

$13 USD om 4 dager

4,9

(416 omtaler)

7,8

@rohi1710rohi1710

Hi , I am working as FPGA design engineer since last 7 years and I have expertise in both verilog and VHDL. I can help you in this project

$12 USD om 15 dager

4,9

(5 omtaler)

4,6

@Ars4r3Lancing

Project: Using DDR3 RAM on Zynq with Vivado + VHDL No problem, lets chat Sir Br, RB

$15 USD om 15 dager

4,9

(7 omtaler)

3,6

@TechnocracyGopi

Hello There, I am a professional working in the same field. I use Vivado 2014.1. I can take care of your task. Please let me know what will be source of data or you want to write some dummy data? Thanks, Gopi

$16 USD om 10 dager