LOGICAL EFFORT: IMPLEMENTATION OF LOGICAL EFFORT TECHNIQUE IN CMOS CIRCUITS

Designing a circuit to achieve the greatest speed or to meet a delay constraint presents a bewildering array of choices. The method of logical effort is an easy way to estimate delay in a cmos circuit. We can select the fastest candidate by comparing delay estimates of different logic structures. The method also specifies the proper number of logic stages on a path and the best transistor sizes for the logic gates. The purpose is the implementation of logical effort technique in CMOS logic gates and further in circuits like basic conventional adder, array multiplier, decoder and multiplexer. So if its transistors sizing changed or adjusted such that its delay reduce then as a result of this bigger circuits also get the benefit of this changes. The aim of the project is described in following steps: [login to view URL] using layout+circuit simulation tool( MAGIC+NGSPICE), to make layout of simple gates(inverter, and, nand, or, nor), and do post-layout timing analysis to verify if the delay of the gate is near what you estimated. [login to view URL] use the method of logical effort to work out W/L of all transistors in some combinational circuit (eg. a 4x16 decoder) on paper. Then to actually do the layout, netlist extraction and timing analysis to verify that the delay you estimated using the method is approximately same. 3. To design a sequential circuit. To do timing analysis separately on flip flops and the combinational blocks between them. Estimate setup and hold times, calculate clock time period for correct operation of the circuit. Show correct operation of the circuit in simulation. Example circuit : pipelined multiplier, or datapath of a simple processor with only 4 instructions (add, and, or, not).