Implement RSA algorithm synthesized code (512 bit) in Verilog

₹600-1500 INR

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omtrent 6 år siden

₹600-1500 INR

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Hi, I would like to implement RSA algorithm synthesized code in Verilog up to 512 bit of encryption. - Encryption data output size can vary from 16-bit to 512 bits. - Prime number generation: two random prime number generated through LFSR and should be stored in FIFO - For every iteration different public and private key pairs should be produced. Kindly contact know if this can be done within 2 days of time frame. We can discuss about budget. Thanks, Jayesh

Engineering

FPGA

Verilog / VHDL

Prosjekt-ID: 16362243

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Aktiv 6 år siden

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9 frilansere byr i gjennomsnitt ₹6 964 INR for denne jobben

@ahmedmohamed85

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₹27 777 INR om 2 dager

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@raulbehl

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₹600 INR om 3 dager

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@awaismqsd

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₹11 111 INR om 14 dager

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@sahaspatha

I am an experienced RTL designer in one of the product companies. I have good experience in building complex digital systems. Pls. consider my bud.

₹1 300 INR om 2 dager

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@imad077

Hey, I have an experience in cryptography and it seems doable in two days so please contact me for more details.

₹4 444 INR om 2 dager

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@ductt

I could locate 4h per day to work on this project. expert on Verilog design & FPGA. Available platform for testing & simualtion. Relevant Skills and Experience worked in large company, expertise in Verilog design for GPU/Ethernet, also implement FPGA system for 25Gs Ethernet

₹2 250 INR om 2 dager