Bias Network Design using Cadence Spectre (Analog Integrated Circuit Design)

Design a bias network using Cadence Spectre (or other CAD software as longs as I can easily follow your steps). Must generate a 10uA current with gm = 100uS that cannot vary by more than +-10% over -40 C to 130 C or supply variations of +-10% with a nominal 1.8V supply. You come up with the idea of using a constant gm bias circuit to bias the amplifier. Design the bias network and determine the dimensions of all transistors. Due to area constraints, you can only use a resistor up to 40K Ohms and a maximum L of 10um. Also, do not forget that K > 20 is forbidden and your circuit needs a startup circuit! (Hint: Consider using m=4 to simplify your equations.) What is required: 1) Schematic annotated with the operating point (THIS ONE IS THE MOST IMPORTANT ONE) 2) Transient Simulation showing correct startup (ramp VDD from 0 to 1.8V) 3) Sweeps showing that gm is stable over the temperature and voltage range. DEADLINE: November 14, 2018 @ 4:00 AM PST (San Diego, California, United States of America) I will give more details to those who bid.