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    2,000 cyclon vhdl project jobber funnet, priser i USD
    Error Emulation model Avsluttet left

    design a structural 16-bit floating point adder and integrate it with error-injection model(VHDL)

    Verilog / VHDL
    $250 (Avg Bid)
    $250 Snitt bud
    1 bud
    By nå
    vhdl for fft (parallization and optimization) Avsluttet left

    design fpga by write c++ code and VHDL code for fast fourier transform algorithm with best optimization and parallelization

    C-programmering FPGA Verilog / VHDL
    $105 (Avg Bid)
    $105 Snitt bud
    2 bud
    By nå
    Project for ahmedmohamed85 Avsluttet left

    Hi Ahmed, we have an immediate need for debugging codes written in VHDL for FPGA device. Please contact us.

    Elektrisk ingeniørvitenskap Elektronikk Ingeniørvitenskap Microcontroller Verilog / VHDL
    $150 (Avg Bid)
    $150 Snitt bud
    1 bud
    By nå
    Write some Software Avsluttet left

    Need someone who is familiar with VHDL software written for FPGA devices. There is a bug in the software that was written that has to be debugged.

    PHP Programvarearkitektur
    $238 (Avg Bid)
    $238 Snitt bud
    6 bud
    By nå
    QuestaSim Debug Some Code Avsluttet left

    The task is to debug and simulate some simple code in VHDL by using QuestaSim.

    FPGA Verilog / VHDL
    $94 (Avg Bid)
    $94 Snitt bud
    14 bud
    By nå
    Real Time Software Engineer Avsluttet left

    Systems and Software projects Technical Responsible Real Time embedded SW development and validation for space microprocessors: Low level SW integration within microprocessors / FPGA solutions Hardware dependent software, communication drivers and protocols Real time multithread applications Integration of VHDL modules for Real Time requirements (VHDL & SW) SW Systems modeling and validationRequirements: Education:Bachelor’s Degree in Computer Engineering, Computer Science, Telecommunication Engineer or other similar Technical discipline. Advanced degree or an equivalent combination of education and experience a plus. Required Experience/Skills: Three (3) or more years of experience in Real Time software development in C/C++. Strong knowledge of embedded real time s...

    App Developer HTML Mobile App Development PHP Sharepoint
    N/A
    N/A
    0 bud
    By nå
    Design a 8x8 DCT and IDCT for JPEG Avsluttet left

    i need a 8x8 DCT and IDCT designed in VHDL

    Verilog / VHDL
    $61 (Avg Bid)
    $61 Snitt bud
    6 bud
    By nå
    FPGA Framework Xilinx Avsluttet left

    ...shall be designed for a Kintex UltraScale Devboard; The main functionality of this system is a pattern generator and an acquisition system. The System shall be controlled from Matlab through an API running simple commands/functions communicating with the FPGA through UART and Ethernet (full support in both). The outcome of the project shall be an environment that is easy to maintain and develop further. The FPGA shall implement an infrastructure consisting of JTAG, Timers, DDR, UART, Ethernet, BRAM, Registers, Microblaze etc. The AXI Ethernet and DMA from Xilinx shall be used in the design, see i.e. page 70 in: Host Computer

    Elektronikk Innebygd programvare FPGA Matlab and Mathematica Verilog / VHDL
    $705 (Avg Bid)
    $705 Snitt bud
    5 bud
    By nå
    16-bit floating point adder Avsluttet left

    Design a 16-bit floating adder in VHDL. Modelsim for simulation and quartus for synthesis

    Verilog / VHDL
    $155 (Avg Bid)
    $155 Snitt bud
    1 bud
    By nå
    Software Implementation Of Rijndael AES High Throughput 128 bit Avsluttet left

    I need to implement a program about Rijndael AES for High Throughput using 128 bit. Identification of critical design parameters, the finalised partitioning system design together with Register Transfer Level (RTL) VHDL description of the critical modules. I need to implement full functionable system of this including all parts of Rijndael AES - Subbytes, Shift rows, Mix columns and Add round key price is still negotiable up to 50GBP. bonus will be awarded to efficiency

    Verilog / VHDL
    $74 (Avg Bid)
    $74 Snitt bud
    6 bud
    By nå
    Write some Software Avsluttet left

    Hello, I need to design a PWM adjustable frequency and duty cycle using FPGA. I'm using the VHDL language and Xilinx ISE 11.

    PHP Programvarearkitektur
    $3 / hr (Avg Bid)
    $3 / hr Snitt bud
    2 bud
    By nå
    Write some Software Avsluttet left

    you are required to develop and test a simple microprocessor using VHDL

    C-programmering Ingeniørvitenskap Programvarearkitektur
    $323 (Avg Bid)
    $323 Snitt bud
    14 bud
    By nå
    Matrix Multiplier Core Design VHDL Avsluttet left

    The project must meet certain requirements. Firstly the project (VHDL design and VHDL testbench must be free of syntax errors. The VHDL project must synthesise with no problems, such as non-synthesisable code, latch inferred and multi-driver. Must show correct results from behavioural simulation and post-route simulation, in which the post-route delay can be observed. Must have the best coding quality with effective hardware resource consumed and efficient processing speed achieved. Must include notes on each section or line indicating processes and stages of code and what they are used for and how they are used.

    PHP Programvarearkitektur Verilog / VHDL
    $108 (Avg Bid)
    $108 Snitt bud
    2 bud
    By nå
    VHDL Programming Avsluttet left

    I need some code written for a Papilio one 250K FPGA board. Code functionality is as follows Generate 3 waveforms inside the FPGA 50HZ sine wave 600HZ triangle waveform Inverse of the 600HZ triangle waveform Overlay and compare all waveforms When non inverted triangle waveform is less than Sine wave generate a logic high digital signal called “LP” When inverted triangle waveform is greater than Sine wave generate a logic high digital signal called “RP”

    Verilog / VHDL
    $126 (Avg Bid)
    $126 Snitt bud
    9 bud
    By nå
    Interfacing DDR3 sdram in zynq using vivado vhdl Avsluttet left

    I want to store some date in the ddr memory on zynq PS using axi connections and read the data back from memory.

    Verilog / VHDL
    $423 (Avg Bid)
    $423 Snitt bud
    4 bud
    By nå
    VHDL Floating Point Adder Avsluttet left

    design a 4-bit floating point adder(specify number of flip flops used)

    Verilog / VHDL
    $119 (Avg Bid)
    Viktig
    $119 Snitt bud
    5 bud
    By nå
    Sequence detector Avsluttet left

    Implementation of a sequence detector in VHDL with technical report. The sequence will be entered using push buttons, these buttons will need to be debounced at a clock cycle specified by the user. More details to be discussed upon bidding.

    FPGA Verilog / VHDL
    $27 (Avg Bid)
    $27 Snitt bud
    6 bud
    By nå
    Basic VHDL coding for simple processor Avsluttet left

    Hello, we need simple VHDL coding for register/memory and buses for a simple processor. Codding and simulation in modelsim. I will send you documents after bid.

    Verilog / VHDL
    $154 (Avg Bid)
    $154 Snitt bud
    7 bud
    By nå
    FIR in VHDL. Avsluttet left

    I need to implement a FIR with 32 programmable coefficients in Vhdl. Should handle 4x inputs.

    Matlab and Mathematica Verilog / VHDL
    $146 (Avg Bid)
    $146 Snitt bud
    21 bud
    By nå
    Sequence detection vhdl Project Avsluttet left

    I have a vhdl project involving sequence detection. if you are familiar with vhdl for altera boards then apply.

    Elektrisk ingeniørvitenskap Elektronikk FPGA Verilog / VHDL
    $6 / hr (Avg Bid)
    $6 / hr Snitt bud
    13 bud
    By nå
    Image processing FPGA algorithm Avsluttet left

    Implement an image face detection detection algorithm in FPGA using VHDL/ Verilog and also writing a MATLAB code to implement the same.

    C-programmering C++ Programmering FPGA Matlab and Mathematica Verilog / VHDL
    $206 (Avg Bid)
    $206 Snitt bud
    15 bud
    By nå
    Matrix Multiplier Core Design_VHDL Avsluttet left

    The project must meet certain requirements. Firstly the project (VHDL design and VHDL testbench must be free of syntax errors. The VHDL project must synthesise with no problems, such as non-synthesisable code, latch inferred and multi-driver. Must show correct results from behavioural simulation and post-route simulation, in which the post-route delay can be observed. Must have the best coding quality with effective hardware resource consumed and efficient processing speed achieved. Must include notes on each section or line indicating processes and stages of code and what they are used for and how they are used.

    Matlab and Mathematica PHP Programvarearkitektur Verilog / VHDL
    $180 (Avg Bid)
    $180 Snitt bud
    14 bud
    By nå
    Optimization of huffman compression code for image compression in matlab and translate the code in vhdl Avsluttet left

    This project is an optimization off the huffman compression , is the code the function "huffmanenco" should not be used so , the idea is o built a code that have a compression ratio better then the one using "huffmanenco" i already have the code with this function,what i want is an optimization of the huffman compresion code without using the function"huffmanenco"and that have a good compression ratio,this code should be written in matlab,then transfered to vhdl from matlab

    Matlab and Mathematica Verilog / VHDL
    $237 (Avg Bid)
    $237 Snitt bud
    7 bud
    By nå
    IFF Test Equipment Avsluttet left

    We have plan development for Avionics Test equipment. We are looking RF, Digital Process, C++ , VHDL Engineer. Especially, Radar engineer If you have Technics feel free to contact to me.

    C-programmering Digital Design
    $3988 (Avg Bid)
    $3988 Snitt bud
    10 bud
    By nå
    SPGA code for pulse generation Avsluttet left

    need a VHDL code for, SPGA for pulse generation. 50Hz, 0.01s delay and 10% duty cycle pulse.

    FPGA
    $86 (Avg Bid)
    $86 Snitt bud
    11 bud
    By nå
    Vlsi Project -- 2 Avsluttet left

    I need two projects on VLSI design using verilog/vhdl language with complete coding and documentation.

    Verilog / VHDL
    $124 (Avg Bid)
    $124 Snitt bud
    28 bud
    By nå
    image processing fpga implementation Avsluttet left

    i have an fpga algorithm fully compatible for conversion to verilog. vhdl. i need some expert to define the acticture re assemble it and test it on fpga. i have some verilog implementation code for it too.

    Elektrisk ingeniørvitenskap Medisinsk skriving PDF Rapportskriving Teknisk skriving
    $150 (Avg Bid)
    $150 Snitt bud
    1 bud
    By nå
    QSD adder and multiplier by VHDL Avsluttet left

    In this project you have to apply a new methodology and improve the results from the base paper table 6,7,8,9 results(Get the paper from attachment ). You have to design the project at VHDL . FPGA kit will be same as the base paper . So you have to mention in project navigator software Spartan 6, XC6SLX16 device, CSG324 package (6slx16csg324-3).

    Digital Design Elektronikk FPGA PCB Layout Verilog / VHDL
    $91 (Avg Bid)
    $91 Snitt bud
    9 bud
    By nå
    Vhdl/Verilog Project Avsluttet left

    I have complete Project code, It successful compile but its not showing any output, showing zero-zero. Please bid only if you are expert in Verilog.

    Elektronikk Ingeniørvitenskap FPGA Matlab and Mathematica Verilog / VHDL
    $4 / hr (Avg Bid)
    $4 / hr Snitt bud
    28 bud
    By nå
    VHDL: Decode DCF77-Receiver signal and implement a stop watch along with. Avsluttet left

    VHDL: Decode DCF77-Receiver signal and implement a stop watch along with.

    FPGA Verilog / VHDL
    $193 (Avg Bid)
    $193 Snitt bud
    12 bud
    By nå
    fpga verilog vhdl Avsluttet left

    it is described in the file below i need this done in an hour

    FPGA Verilog / VHDL
    $61 (Avg Bid)
    $61 Snitt bud
    1 bud
    By nå
    fpga verilog vhdl Avsluttet left

    it is described in the file below i need this done in an hour

    FPGA Verilog / VHDL
    $89 (Avg Bid)
    $89 Snitt bud
    9 bud
    By nå
    ZYNQ VHDL design using Microzed / MAX10 design Avsluttet left

    Final outcome required : A system that takes images from a image sensor (OnSemi Python300) at 100FPS and stores them on a memory card and also runs Linux and is interactive through a touchscreen. As per my finding, it is best developed using ZYNQ. MAX10 FPGA with NIOSII is a...developed using ZYNQ. MAX10 FPGA with NIOSII is also a good choice. Current position: Avnet has made available the IP for interfacing the image sensor. So the bulk of work is done already. A designer is need who can take the IP and build the rest of the system. Relevant links will be shared during discussions. Since the most difficult part (the image sensor interfacing) is done already, this project shouldn't take much more than a week or so. Hence please quote your prices accordingly. Milestone pay...

    FPGA Verilog / VHDL
    $210 (Avg Bid)
    $210 Snitt bud
    3 bud
    By nå
    Write some Software in VHDL Avsluttet left

    I need some help to write a very simple code in VHDL. This work includes: combinacional circuits, state machine, gray code and flip flops.

    Programvarearkitektur Verilog / VHDL
    $15 (Avg Bid)
    $15 Snitt bud
    13 bud
    By nå
    help in vhdl programming with simulation Avsluttet left

    writing algorithm in vhdl code with simulation

    Algoritme Verilog / VHDL
    $27 (Avg Bid)
    $27 Snitt bud
    14 bud
    By nå
    Write a Report Avsluttet left

    ...this carefully, different items are required for a research paper review versus a project):rnrnIntroductionrnrno Provide an introduction to the topic of your project/research paper.rno Provide background information about the main concepts of your project/research paper.rn--This will include background about testing concepts as well as the application rnwhich your project/research paper examinesrno Explain the importance (related to VLSI testing) of your project/research paper and how it complements what we have discussed in class.rnrnBodyrnrno For a project:rn-- Summarize each step of your procedure in completing your project (e.g. What was the design process for your project?, What revisions to yo...

    Rapportskriving
    $56 (Avg Bid)
    $56 Snitt bud
    7 bud
    By nå
    assembly, C, embedded software, verilog/vhdl Avsluttet left

    Assembly project with circuit design.

    Assembly C-programmering Innebygd programvare Verilog / VHDL
    $40 (Avg Bid)
    $40 Snitt bud
    1 bud
    By nå
    Electronic VHDL Avsluttet left

    I have 4 tasks related to Digital logic design. I need help with them. Please bid if you know VHDL.

    Elektrisk ingeniørvitenskap Elektronikk Ingeniørvitenskap Telekommunikasjonsteknikk
    $73 (Avg Bid)
    $73 Snitt bud
    20 bud
    By nå
    fm design radio Avsluttet left

    rnfollowing blocks need to be implemented IN VHDL with their test bench - read_iq, demod, decimating FIR, Deemph, qarctan rnrnthe module should be synthesizable and implemented with FIFO rnrnwith following conditions -rnrnC macros should be implemented as inlined VHDL functionsrnUse the same quantization bit width as in the software.rnCreate a package with the array of filter coefficients and use generics to configure the filter taps and coefficients.rnHigh-level for-loops can be eliminated and replaced with streaming FIFOsrnUnroll internal function loops completely where applicable, such as shift registersrnApply one or more optimizations, such as loop unrolling or pipelining where applicablernImplement the division algorithm discussed in class for...

    Verilog / VHDL
    $451 (Avg Bid)
    $451 Snitt bud
    3 bud
    By nå
    simple brute LCM calculator design in VHDL Avsluttet left

    to make a lowest common multiple design based on the c++ code given to me. Must also complete the ASM chart and datapath

    Elektrisk ingeniørvitenskap Ingeniørvitenskap FPGA Verilog / VHDL
    $138 (Avg Bid)
    $138 Snitt bud
    7 bud
    By nå
    FM Radio Design Avsluttet left

    In this assignment, you will be building a streaming FM Stereo Radio. rnrnUsing the attached C software model, you will need to implement each of the function blocks in VHDL. Compile the software and run the input USRP data to see how the FM radio works. If you're on a Mac, you may need to adjust the header files and/or the soundcard interface. Use the "whereis" command to locate the headers. I recommend using visual studio to compare the inputs/outputs of each functional unit.rnrnIn your design, you should employ the following strategies:rnrnC macros should be implemented as inlined VHDL functionsrnUse the same quantization bit width as in the software.rnCreate a package with the array of filter coefficients and use generics to configure the...

    Verilog / VHDL
    $39 / hr (Avg Bid)
    Viktig
    $39 / hr Snitt bud
    3 bud
    By nå
    VHDL code for DCT and IDCT Avsluttet left

    16x16 image to DCT store in a RAM/ROM and do IDCT to get back original 16x16 image.

    Verilog / VHDL
    $12 / hr (Avg Bid)
    $12 / hr Snitt bud
    8 bud
    By nå
    VHDL Expert Needed Avsluttet left

    I need help in Analogue and Digital Electronics which involves vhdl as well. i will share details later. Thanks Its simple project. happy bidding..

    Circuit Design Elektrisk ingeniørvitenskap Elektronikk FPGA Verilog / VHDL
    $6 / hr (Avg Bid)
    $6 / hr Snitt bud
    13 bud
    By nå
    Make changes to a verilog code -- 2 Avsluttet left

    Hi, I am looking for someone with experience in verilog/VHDL programming or with Electronics background to modify some code. Details and files will be given in chat in what needs to be done in the code.

    Elektronikk Innebygd programvare Verilog / VHDL
    $24 (Avg Bid)
    $24 Snitt bud
    5 bud
    By nå
    FSM + D: Factorial Computation VHDL -- 2 Avsluttet left

    The objective of this lab is to implement, in VHDL, an FSM+D single purpose processor that will evaluate the factorial of n. Copy the code and simulation image on a word document. The details of the project are in the attached word document

    Digital Design Elektrisk ingeniørvitenskap Elektronikk Verilog / VHDL
    $50 (Avg Bid)
    $50 Snitt bud
    1 bud
    By nå
    FSM + D: Factorial Computation VHDL Avsluttet left

    The objective of this lab is to implement, in VHDL, an FSM+D single purpose processor that will evaluate the factorial of n. Copy the code and simulation image on a word document. The details of the project are in the attached word document

    Digital Design Elektrisk ingeniørvitenskap Elektronikk Verilog / VHDL
    $44 (Avg Bid)
    $44 Snitt bud
    1 bud
    By nå
    VHDL and Quartus II Avsluttet left

    Knowledge on MULTIPLEXERS, Concurrent behavioral VHDL description of a SN74F153, IEEE. Need to answer three questions.

    Elektrisk ingeniørvitenskap Ingeniørvitenskap Programvarearkitektur
    $22 (Avg Bid)
    $22 Snitt bud
    6 bud
    By nå
    Assignment on digital systems and VHDL design Avsluttet left

    Assignment on VHDL design. I have Some problems . I think 12 problems and I need solutions to those problems and I can give u 2 days.

    AutoCAD Digital Design Verilog / VHDL
    $123 (Avg Bid)
    $123 Snitt bud
    24 bud
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    Manufacture a Product for me Avsluttet left

    Dear sir/maam, I have a job experience in VLSI design ,i am good in VHDL,VERILOG

    Elektronikk Innebygd programvare Verilog / VHDL
    $15 (Avg Bid)
    $15 Snitt bud
    1 bud
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    vhdl project -- ---- Avsluttet left

    i need vhdl expert for my short vhdl project. details will be provided to suitable candidate

    Elektrisk ingeniørvitenskap FPGA Verilog / VHDL
    $11 / hr (Avg Bid)
    $11 / hr Snitt bud
    2 bud
    By nå
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