Verilog / VHDL Jobs

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Om Verilog / VHDL
Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Ansett Verilog / VHDL Designers

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    16 jobber funnet, priser i USD
    Creating Circuit in Logisim 6 dager left
    VERIFISERT

    Build a calculator that can add and subtract decimals of up to 5 decimal digits. The calculator should have a display of 6 decimal digits. There should a number pad with digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 and three possible operations, + (addition), - (subtraction), = (equals). The flow of the operations should be as follow: While typing the number it should be displayed right aligned, extendin...

    Circuit Design Elektrisk ingeniørvitenskap Elektronikk Ingeniørvitenskap Verilog / VHDL
    $59 (Avg Bid)
    $59 Snitt bud
    5 bud
    By nå
    embedded system, circuit designing,schematic 5 dager left

    i want to hire experienced person of circuit designing and in embedded system contact me for more information chate

    Circuit Design Elektrisk ingeniørvitenskap Microcontroller PCB Layout Verilog / VHDL
    $374 (Avg Bid)
    $374 Snitt bud
    23 bud
    By nå
    Vhdl project 5 dager left

    It is a cluster related vhdl project.

    C-programmering Elektrisk ingeniørvitenskap Ingeniørvitenskap FPGA Verilog / VHDL
    $283 (Avg Bid)
    $283 Snitt bud
    12 bud
    By nå
    fpga expert needed to finish a small project 5 dager left

    i already have the 90% of the code just need to finish 10% and guide me on running the code my my board

    Elektrisk ingeniørvitenskap Elektronikk FPGA Microcontroller Verilog / VHDL
    $60 (Avg Bid)
    $60 Snitt bud
    6 bud
    By nå
    I need FPGA expert for a small parking system project using ir sensors on nexsys 2 spartan 3e board 4 dager left

    this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

    Arduino Elektrisk ingeniørvitenskap Elektronikk FPGA Verilog / VHDL
    $142 (Avg Bid)
    $142 Snitt bud
    5 bud
    By nå
    Development of hardware solutions on CPU, GPU & FPGA for 2-D Phase Unwrapping algorithm 4 dager left

    Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results should be demonstrated on MATLAB by comp...

    Ingeniørvitenskap Matlab and Mathematica Verilog / VHDL
    $139 (Avg Bid)
    $139 Snitt bud
    2 bud
    By nå
    VLSI CMOS simple project urgent $50 -- 2 2 dager left

    hi ineed vlsi cmos expert asap

    Circuit Design Digital Design Elektrisk ingeniørvitenskap Elektronikk Verilog / VHDL
    $39 (Avg Bid)
    $39 Snitt bud
    6 bud
    By nå
    MRAS SYSTEM SIMULATION USING SIMULINK 1 dag left
    VERIFISERT

    MRAS SYSTEM SIMULATION USING SIMULINK NEEDED You will have 7 days to complete the work defined in scope. Your bid will not be negotiated so please read well before you bid. Payment will be 50/50 after simulation and after writting. Maximum Budget is 250USD

    Elektrisk ingeniørvitenskap Elektronikk Ingeniørvitenskap Matlab and Mathematica Verilog / VHDL
    $380 (Avg Bid)
    $380 Snitt bud
    7 bud
    By nå
    VHDL FPGA GAME IMPLEMENTATION 1 dag left

    VHDL implemented in altera de2 board

    Elektrisk ingeniørvitenskap Elektronikk FPGA Microcontroller Verilog / VHDL
    $349 (Avg Bid)
    $349 Snitt bud
    5 bud
    By nå
    QUARTUS II (ALTERA DE2 - FPGA VHDL) 1 dag left

    Our group wants to implement a game using altera de2 cyclone ii board. Please see the attached file for the details of the game to be implemented.

    Elektrisk ingeniørvitenskap Elektronikk FPGA Microcontroller Verilog / VHDL
    $78 (Avg Bid)
    $78 Snitt bud
    3 bud
    By nå
    write vhdl code for a simple basic processor with control unit 1 dag left

    A very simple processor is designed, need to write vhdl codes(few components already written) for it and implement the microprogrammed Control unit.

    Elektronikk FPGA Microcontroller Verilog / VHDL
    $24 (Avg Bid)
    $24 Snitt bud
    6 bud
    By nå
    I need a microcontroller developer 1 dag left

    The project has a few basic functions. 1. maintain a specific temperature 2. fire a signal to a solenoid valve in particular (adjustable) intervals. other basic functions like on off etc

    Arduino Elektrisk ingeniørvitenskap Elektronikk Microcontroller Verilog / VHDL
    $190 (Avg Bid)
    $190 Snitt bud
    43 bud
    By nå
    Verilog simulation of two action-reaction processes 23 dager left
    VERIFISERT

    Verilog simulation of two action-reaction processes

    Digital Design Elektrisk ingeniørvitenskap Electronic Design Matematikk Verilog / VHDL
    $29 (Avg Bid)
    $29 Snitt bud
    6 bud
    By nå
    multi level parking system by using VERILOG in Xilinks and Nexys2 FPGA 9 dager left

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    Elektrisk ingeniørvitenskap Elektronikk FPGA Microcontroller Verilog / VHDL
    $177 (Avg Bid)
    $177 Snitt bud
    7 bud
    By nå
    adc data decoding module 1 time left

    Design adc data decoding module. (vivado 2018.2) Input: FCLK,DCLK,DATA_0~DATA_15.(all input signals are LVDS) Output: CLKOUT, DOUT_0 [15:0] ~ DOUT_31 [15:0]. One data path contains two adc signals. The two adc signals are distinguished by FCLK level. I need to decode the adc data into 16-bit wide data and output a total of 32 channels of adc data. The input waveform is shown in the figure. The dif...

    Elektronikk FPGA Microcontroller Verilog / VHDL
    $246 (Avg Bid)
    $246 Snitt bud
    9 bud
    By nå
    Anyone expert in vhdl Avsluttet left

    Vhdl is needed

    Verilog / VHDL
    $27 (Avg Bid)
    $27 Snitt bud
    6 bud
    By nå
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