Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Ansett Verilog / VHDL Designers

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    21 jobber funnet, priser i USD

    I need you to develop some software for me. I would like this software to be developed for Windows.

    $45 (Avg Bid)
    $45 Snitt bud
    4 bud
    linux build for zynq board 6 dager left
    VERIFISERT

    https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841738/Getting+Started [logg inn for å se URL] (Petalinux) Linux build and application development for simple LED blink project. Someone with good FPGA/SoC embedded development experience.

    $180 (Avg Bid)
    $180 Snitt bud
    3 bud
    router design 6 dager left
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    Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design

    $21 - $174
    $21 - $174
    0 bud
    Analog cmos VLSI Design 6 dager left
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    Full custom design of Sense Amplifier Half-Buffer for asynchronous VLSI Design.

    $208 (Avg Bid)
    $208 Snitt bud
    2 bud

    Hi, I need FPGA HCS08 Expert we will be using HCS08 DE1 MicroController. more details i will share in chat box. please if you have experience relegated to this bid. thanks.

    $174 (Avg Bid)
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    5 bud
    Need to build design in FPGA board 6 dager left
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    Need to build design in FPGA board

    $171 (Avg Bid)
    $171 Snitt bud
    6 bud
    VHDL Circuit Design and Simulation 6 dager left
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    VHDL Circuit Design and Simulation

    $165 (Avg Bid)
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    18 bud
    General purpose regester 5 dager left
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    complete the design of a simple general purpose processor using Xilinx ISE Schematic Capture.

    $197 (Avg Bid)
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    8 bud

    finite-state synchronous machines mealy and moore machine for given task, using Intel Quartus.

    $181 (Avg Bid)
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    15 bud

    Hello, I need to create a project in VHDL: a simple operations calculator (addition, subtraction, multiplication, and division). The result have to be displayed on the PmodCLP I need this to implement on the board NEXYS 4, Artix 7 FPGA. The VHDL code should be developed in Xilinx ISE. I would need the documentation. Also include as many comments as you can about what is going on so that I can...

    $210 (Avg Bid)
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    3 bud

    Hello, I need to create a project in VHDL: a simple operations calculator (addition, subtraction, multiplication, and division). The result have to be displayed on the PmodCLP I need this to implement on the board NEXYS 4, Artix 7 FPGA. The VHDL code should be developed in Xilinx ISE. I would need the documentation. Also include as many comments as you can about what is going on so that I can...

    $220 (Avg Bid)
    $220 Snitt bud
    8 bud

    PCle, ethernet , UVM, System Verilog

    $200 (Avg Bid)
    $200 Snitt bud
    2 bud

    We plan to use the Sny IMX420 imager, the Framos IP Core and a Xilinx FPGA. Looking for a vision software freelancer with experience in these technologies. Vivado 2018 or later.

    $53 / hr (Avg Bid)
    $53 / hr Snitt bud
    10 bud

    The first installment of the project dealt with the capability to simulate the actions of four very simple gate types, an INV gate, an AND gate, an OR gate and an XOR (exclusive or) gate. The second installment extended that capability by describing the simple logic gates using Verilog, but the Verilog was restricted to descriptions of circuits which only contained a single gate. For the third ins...

    $61 (Avg Bid)
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    12 bud
    Make an interface for a MIPS Game 2 dager left
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    *CHEAPEST BID WILL WIN* I need someone to code an interface for a game similar to minesweeper in MIPS. The logic and everything is provided, all I need someone is to complete the interface. This sounds very complicated but it's an easy job, and that's why this comes under micro project. Files and more details will be provided over chat.

    $43 (Avg Bid)
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    3 bud
    Project in system verilog 2 dager left
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    Build a project using system verilog

    $190 (Avg Bid)
    $190 Snitt bud
    12 bud

    finite-state synchronous machines mealy and moore machine for given task.

    $130 (Avg Bid)
    $130 Snitt bud
    21 bud

    Need to investigate the latches, flip-flops and the registers in VHDL laboratory work

    $69 (Avg Bid)
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    10 bud

    digital Alarm clock. I need it for my final project. Please let me know if anyone can do it in 20$. Lowest bit will be rewarded.

    $53 (Avg Bid)
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    11 bud

    I need it for my final project. Please let me know if anyone can do it in 20$. Lowest bit will be rewarded.

    $28 (Avg Bid)
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    7 bud

    This Project is to investigate latches, flip-flops and registers. VHDL -- Quartus Prime Lite 18.1 Quartus.

    $15 (Avg Bid)
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    3 bud