Verilog / VHDL Jobber og konkurranser
Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers.
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| Prosjekt/Konkurranse | Beskrivelse | Bud/Bidrag | Ferdigheter | Startet | Avsluttes | Pris (USD) | |
|---|---|---|---|---|---|---|---|
| VLSI design and testability using SPICE/ Verilog/VHDL | An applied project may involve using tools such as Spice, Verilog/VHDL, etc. to demonstrate its success | 3 | Verilog / VHDL, Very-large-scale integration (VLSI) | Oct 20, 2017 | I dag6d 15t | $509 | |
| Logisim Software Tasks | Hi I need someone who is good with Logisim Software to complete some tasks. | 7 | Ingeniørvitenskap, Elektronikk, Verilog / VHDL, Elektrisk ingeniørvitenskap | Oct 20, 2017 | I dag6d 10t | $27 | |
| Power Generation Simulation using LabVIEW | Power Generation Simulation using LabVIEW. Power generation stations will often consist of a number of individual generators where each generates a proportion of the overall station’s output. Need two separate applications. Application 1 and Application 2. | 6 | Matlab and Mathematica, Verilog / VHDL, Elektrisk ingeniørvitenskap, LabVIEW, Arduino | Oct 20, 2017 | I dag6d 2t | $54 | |
| Digital design using Verilog | Use Basys 3 Board and Vivado 2016.2 I'll share the rest details | 7 | Verilog / VHDL, Microcontroller, Elektrisk ingeniørvitenskap, LabVIEW, FPGA | Oct 20, 2017 | I dag6d 1t | $42 | |
| VHDL Radio Clock + python script | Need help in VHDL everything is mentioned on the PDF | 6 | Elektronikk, Verilog / VHDL, Testing av programvare, Elektrisk ingeniørvitenskap, FPGA | Oct 19, 2017 | Oct 19, 20175d 4t | $71 | |
| Project for Gabriel G. | I need help with capsim practice rounds | 4 | Prosjektledelse, Telefonsalg, Excel, Matlab and Mathematica, Verilog / VHDL | Oct 18, 2017 | Oct 18, 20174d 17t | $25 | |
| verilog project | making verilog on quartus II (cyclone IV) | 11 | Ingeniørvitenskap, Verilog / VHDL, Programvarearkitektur, Assembly, FPGA | Oct 18, 2017 | Oct 18, 20174d 11t | $145 | |
| Cloudsim project | I want someone to work on programming part in cloudsim that includes migration, Placement, scheduling and power consumption. | 2 | C-programmering, Java, Verilog / VHDL, Programvarearkitektur, C++ Programmering | Oct 18, 2017 | Oct 18, 20174d 1t | $61 | |
| Verilog programming - 18/10/2017 00:34 EDT | Simple verilog programming project. Create an ALU with full [url fjernet, logg inn for å se] is desired is a Verilog system that can operate as a calculator with a set of logic gates attached. Other details provided later. | 13 | Verilog / VHDL | Oct 18, 2017 | Oct 18, 20173d 23t | $96 | |
| Verification Of Motion Estimator Using UVM | Verification Of Motion Estimator Using UVM(Universal Verification Methodology) | 5 | Verilog / VHDL, Elektrisk ingeniørvitenskap, Very-large-scale integration (VLSI) | Oct 17, 2017 | Oct 17, 20173d 22t | $238 | |
| Verilog programming | Simple verilog programming project. Create an ALU with full [url fjernet, logg inn for å se] is desired is a Verilog system that can operate as a calculator with a set of logic gates attached. Other details provided later. | 5 | Verilog / VHDL | Oct 17, 2017 | Oct 17, 20173d 19t | $89 | |
| ASIC Design in Verilog | This project is related to Computational Neural Networks | 2 | Matlab and Mathematica, Verilog / VHDL, Neural Networks | Oct 17, 2017 | Oct 17, 20173d 15t | $153 | |
| VHDL Radio clock | everything is going to be explained on the pdf | 11 | Elektronikk, Verilog / VHDL, Microcontroller, Elektrisk ingeniørvitenskap, FPGA | Oct 17, 2017 | Oct 17, 20173d 14t | $40 | |
| Design of audio visualiser using DE2-115 Altera board | I want to implement an audio visualizer on the screen of the voice spoken through the mic or played using SD card. | 4 | Verilog / VHDL | Oct 17, 2017 | Oct 17, 20173d 12t | $234 | |
| Matlab power system Simulation using Simulink -- 2 - 17/10/2017 07:15 EDT | My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa | 12 | Ingeniørvitenskap, Elektronikk, Matlab and Mathematica, Verilog / VHDL, Elektrisk ingeniørvitenskap | Oct 17, 2017 | Oct 17, 20173d 6t | $136 | |
| Matlab power system Simulation using Simulink | My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa | 9 | Ingeniørvitenskap, Elektronikk, Matlab and Mathematica, Verilog / VHDL, Elektrisk ingeniørvitenskap | Oct 17, 2017 | Oct 17, 20173d 4t | $161 | |
| Elektronikk, Verilog / VHDL, Microcontroller, Elektrisk ingeniørvitenskap, LabVIEW | Oct 16, 2017 | Oct 16, 20172d 23t | |||||
| netlist construction in EE using C++ | refactor the sample code by using the c++ | 9 | C-programmering, Verilog / VHDL, C# Programmering, Elektrisk ingeniørvitenskap, C++ Programmering | Oct 16, 2017 | Oct 16, 20172d 11t | $135 | |
| project for Ahmed M -- 2 - 16/10/2017 12:09 EDT | I believe you must do this project. | 2 | Verilog / VHDL | Oct 16, 2017 | Oct 16, 20172d 11t | $127 | |
| project for Ahmed M | I believe you must do this project. | 2 | Verilog / VHDL | Oct 16, 2017 | Oct 16, 20172d 11t | $155 | |
| verilog project | want verilog code on fpga i want soon | 2 | Ingeniørvitenskap, Verilog / VHDL, Programvarearkitektur, LabVIEW, FPGA | Oct 16, 2017 | Oct 16, 20172d 10t | $8 | |
| ASIC Designs and Development | Hello. I am into a project that involves creating PCB / ASIC design with FPGA/CLPD. The specified ASIC Architecture as a product needs to be able calculate one or more algorithms connected through some type of data socket. Performance and power is important. I am interrested to get in touch with a board designer and vhdl developer that have knowledge both with electrical layouts and vhdl. ... | 6 | Ingeniørvitenskap, Elektronikk, Verilog / VHDL, Elektrisk ingeniørvitenskap, PCB Layout | Oct 16, 2017 | Oct 16, 20172d 4t | $15 | |
| veriloghdl code for calculation area | THis must implement on quartus( altera FPGA cyclone IV) | 4 | C-programmering, Verilog / VHDL, Microcontroller, C++ Programmering, FPGA | Oct 16, 2017 | Oct 16, 20172d 3t | $103 | |
| making verlog hdl code | calculataion area in black and white image on fpga ( cyclone IV) | 8 | C-programmering, Verilog / VHDL, Microcontroller, Elektrisk ingeniørvitenskap, C++ Programmering | Oct 16, 2017 | Oct 16, 20171d 23t | $125 | |
| VHDL Coursework | help in VHDL codes ,, everything will be explained later | 13 | Ingeniørvitenskap, Elektronikk, Verilog / VHDL, Elektrisk ingeniørvitenskap | Oct 15, 2017 | Oct 15, 20171d 15t | $55 | |
| fpga software | I want to read programmes in FPGA chips | 17 | C-programmering, Verilog / VHDL, Programvarearkitektur, FPGA | Oct 15, 2017 | Oct 15, 20171d 9t | $413 | |
| creation of hardware module using verilog which will be able to communicate with the memory of the processor | using Verilog which will be able to communicate with the memory of the processor | 4 | Verilog / VHDL | Oct 14, 2017 | Oct 14, 20179t | $62 | |
| simple verilog hdl code | calculate each area in black and white image | 11 | C-programmering, Ingeniørvitenskap, Verilog / VHDL, Microcontroller, FPGA | Oct 13, 2017 | Oct 13, 2017Avsluttet | $47 | |
| Simple Verilog Project | Design a perception timer that measures the time for a user to respond to a request to complete a simple task. I'll send the rest details for part 3. | 8 | Ingeniørvitenskap, Matlab and Mathematica, Verilog / VHDL, Elektrisk ingeniørvitenskap, FPGA | Oct 13, 2017 | Oct 13, 2017Avsluttet | $24 | |
| Color space conversions and FPGA's | 3 pages report in two parts on: (i) fundamental information about FPGAs and their programming, and (ii) standard color spaces and formulas for converting those color spaces into other ones. (Plagarism free) finished in 3 days maximum. | 9 | Ingeniørvitenskap, Verilog / VHDL, Elektrisk ingeniørvitenskap, FPGA | Oct 13, 2017 | Oct 13, 2017Avsluttet | $66 | |
| Build software | Looking for expert in FPGA and verilog | 18 | C-programmering, Verilog / VHDL, Programvarearkitektur, C++ Programmering, FPGA | Oct 12, 2017 | Oct 12, 2017Avsluttet | $480 | |
| Statcom in simulink Power electronics expert -- 2 | Statcom in simulink Power electronics expert needed | 9 | Elektronikk, Matlab and Mathematica, Verilog / VHDL, Elektrisk ingeniørvitenskap, FPGA | Oct 11, 2017 | Oct 11, 2017Avsluttet | $164 | |
| Want to develop robotic program and test the same with simulation to check feasibility of and automation idea | Existing : Manual labours are lifting filled 25 kg bags from stack of machine palletised load (40 bags per wooden pallet, and loading into trucks, containers. Automation solution : Using three axis gantry robot, vacuum lifting end tool and smart programming to create fully automatic truck loading system. All above only on simulation, 3d models to check feasibility of solutions and then to us... | 5 | Matlab and Mathematica, Verilog / VHDL, Programvarearkitektur, Programvareutvikling, Programming | Oct 11, 2017 | Oct 11, 2017Avsluttet | $4680 | |
| VLSI PROJECTS | FIND THE ATTACHED IEEE [url fjernet, logg inn for å se] REQUIREMENTS | 4 | Verilog / VHDL, FPGA, Very-large-scale integration (VLSI) | Oct 11, 2017 | Oct 11, 2017Avsluttet | $86 | |
| Statcom in simulink Power electronics expert | Statcom in simulink Power electronics expert needed | 9 | Elektronikk, Matlab and Mathematica, Verilog / VHDL, FPGA | Oct 11, 2017 | Oct 11, 2017Avsluttet | $114 | |
| Convert a code from Aptech Gauss language into Matlab with Parallel processing. | I have a code written in Aptech Gauss program that I want to convert into Matlab and I want the code to run under CUDA power in Matlab. | 3 | Matlab and Mathematica, Verilog / VHDL, Programvarearkitektur, CUDA, Programvareutvikling | Oct 10, 2017 | Oct 10, 2017Avsluttet | $153 | |
| Prelab | Write VHDL code | 7 | Verilog / VHDL | Oct 10, 2017 | Oct 10, 2017Avsluttet | $27 | |
| dimensionality reduction using PCA | we will consider use of PCA for simple dimensionality reduction, i.e., determining the signal subspace when there are more observations than the underlying latent variables—signals. The main assumption here is that both the noise and signals are independent and identically distributed Gaussians, however the the signals are correlated among themselves while the noise components are not, ... | 14 | Matlab and Mathematica, Verilog / VHDL, Finite Element Analysis, CUDA, FPGA | Oct 10, 2017 | Oct 10, 2017Avsluttet | $408 | |
| Altera DE115 - Audio signal processing | Record voice , Add and Remove Noise and play back recording. Design and implement the verilog code on an Altera DE2-115 Development Board. Available Hardware Microphones, Speakers | 9 | Verilog / VHDL, Microcontroller, Innebygd programvare, Assembly, FPGA | Oct 10, 2017 | Oct 10, 2017Avsluttet | $226 | |
| Audio Signal Processing | AIM - Record Audio , Add and Remove Noise and play back audio. To design and implement the Embedded System centred on an Altera DE2-115 Development Board. The project should be based on a Verilog HDL implementation. Available Hardware In addition to the DE2-115 board, the following hardware devices are available. If you wish to do a project requiring hardware support but don’t see the... | 7 | Verilog / VHDL, Microcontroller, Elektrisk ingeniørvitenskap, Innebygd programvare, FPGA | Oct 10, 2017 | Oct 10, 2017Avsluttet | $509 | |
| Sequence Diagram | There is a service class called PurchaseOrder that is called when a customer makes a purchase. It has a public method purchase(Account, Order). It does the following. a. Call [url fjernet, logg inn for å se]() b. Call [url fjernet, logg inn for å se](Account) c. Call [url fjernet, logg inn for å se]() d. [url fjernet, logg inn for å se]() calls [url fjernet, logg inn fo... | 6 | Verilog / VHDL, Programvarearkitektur, PLC & SCADA, Finite Element Analysis, Ingeniørkunst | Oct 10, 2017 | Oct 10, 2017Avsluttet | $37 | |
| Matlab Program for Harmonics Analysis for a sampled data (Data in excel format) | Need a Matlab program to perform Harmonics Analysis for a sampled data (data in Excel format). Matlab Codes must structured to read data from Excel file. Please find the attached Excel file [url fjernet, logg inn for å se] | 22 | Excel, Matlab and Mathematica, Verilog / VHDL, Programvarearkitektur, Programvareutvikling | Oct 7, 2017 | Oct 7, 2017Avsluttet | $22 | |
| UML/MARTE modeling | I want to build an interface(which consists of rules) to transform any MML model to a UML-MARTE model using AGG(algebraic graph transformation). | 1 | Verilog / VHDL, UML-design, Finite Element Analysis, SAS, CATIA | Oct 7, 2017 | Oct 7, 2017Avsluttet | $587 | |
| matlab report making 10 pages minimum | hi discussion via chat no front milestone need it in 12 hrs 10 mages maximum paper should be in IEEE formats no plagiarism is there.. please give a good quote | 10 | Matlab and Mathematica, Verilog / VHDL, LaTeX, Matematikk, Fysikk | Oct 7, 2017 | Oct 7, 2017Avsluttet | $48 | |
| Matlab Write a Function for Forward Kinematics of the RPR Robot | Input Format are the joint angles in radian, as shown in the figure is the extension of the prismatic joint in inches, as shown in the figure Output Format R is a 3x3 rotation matrix representing (Note: where represents a point in frame x) pos is a 4x3 matrix where each row contains the x,y,z coordinates represented as [x y z] in matrix form. Each row is the x,y,z coordinates of a point... | 16 | Matlab and Mathematica, Verilog / VHDL, Programvarearkitektur, Finite Element Analysis, Programvareutvikling | Oct 7, 2017 | Oct 7, 2017Avsluttet | $38 | |
| String compare algorithm | need an algorithm that would compare two long strings delimited by | | 3 | Matlab and Mathematica, Verilog / VHDL, Algoritme , CUDA, Maskinopplæring | Oct 7, 2017 | Oct 7, 2017Avsluttet | $1960 | |
| Cryptoanalysis - Cryptograpgy - C programming | I am looking for someone to write me a code in c that will test the cryptographic strength of the passwords. I can share more specific instructions and dummy passwords. I need a simple program. | 9 | C-programmering, Verilog / VHDL, Programvarearkitektur, Prolog, C++ Programmering | Oct 6, 2017 | Oct 6, 2017Avsluttet | $69 | |
| MSF and DCF receiver | everything will me explained later | 5 | Ingeniørvitenskap, Elektronikk, Verilog / VHDL, Elektrisk ingeniørvitenskap, Binær analyse | Oct 6, 2017 | Oct 6, 2017Avsluttet | $46 | |
| Embedded Control System Design | It is a project on Embedded Control System Design. I will give the details later. | 12 | C-programmering, Verilog / VHDL | Oct 6, 2017 | Oct 6, 2017Avsluttet | $44 | |
| ABAQUS Model (CFRP Beam) | I need to make the results of this ABAQUS model converge with the experimental data curve (shown in the Excel sheet: Load vs Deflection). The current results shows a much higher yield and peak loading compared to the experimental data. The model files are attached to this project. | 13 | Verilog / VHDL, Finite Element Analysis, Datagrafikk, Industriell teknikk, CATIA | Oct 5, 2017 | Oct 5, 2017Avsluttet | $189 |
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