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Matlab and Mathematica
Microcontroller
Verilog / VHDL
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$5 USD / time
EGYPTs flagg
assuit, egypt
$5 USD / time
Det er for øyeblikket 11:34 p.m. her
Ble med mai 22, 2017
1 Anbefaling

Mohammed M.

@funnyman1992

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$5 USD / time
EGYPTs flagg
assuit, egypt
$5 USD / time
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Gjenansettelsesrate

FPGA Designer (VHDL programmer)

I am a navigation, Guidance and Control Engineer having specialization in Electronics and Control with more than 3-years experience. I have Master degree in Engineering with specialization in CONTROL. TOP SKILLS 1. FPGA Design (VHDL), writing VHDL test benches and working with simulators such as ModelSim. 2. Embedded System Design. (Schematic, labview) 3. Software Design. (C/C++/Matlab) 4. Control System Design & Modelling (Continuous, Discrete, Linear, Non-Linear, Optimal, Fuzzy Logic + Matlab & Simulink) 5. Digital System/Logic Design (VHDL, Logisim) 6. Micro-controllers (Arduino, PIC) 7. Control of Electric Machine Drives 8. Circuit Analysis and Designe etc 9. PCB Design (Proteous + Ultiboard + Altium Designer) I have designed many unmanned systems (Ground vehicle, winged aircraft and other remote control systems) using FPGA
Freelancer Engineers Egypt
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Portefølje

4792491
i designed parallel AES that use 2 clock in stead of 26 clock in the normal and 12 in the pipe-lining to increase its performance and speed it.
parallel AES encryption system
i designed parallel AES that use 2 clock in stead of 26 clock in the normal and 12 in the pipe-lining to increase its performance and speed it.
parallel AES encryption system
4792486
i modified the normal AES that uses 26 clock to the pipelining design that use just 12 clock and then i designed the parallel that use 2 clock.
pipelining AES encryption system
i modified the normal AES that uses 26 clock to the pipelining design that use just 12 clock and then i designed the parallel that use 2 clock.
pipelining AES encryption system
4792483
Normal AES encryption system that uses 26 clock to output results,i have modified this design in the pipe-lining design that uses 12 clock and then i modified the design again to use just 2 clock in the parallel design.
Normal AES encryption system
Normal AES encryption system that uses 26 clock to output results,i have modified this design in the pipe-lining design that uses 12 clock and then i modified the design again to use just 2 clock in the parallel design.
Normal AES encryption system
4091670
Designing UAV Using VHDL
Designing unmaned vehicle using FPGA
4091669
Designing UART Protocol
UART Protocol
4792491
i designed parallel AES that use 2 clock in stead of 26 clock in the normal and 12 in the pipe-lining to increase its performance and speed it.
parallel AES encryption system
i designed parallel AES that use 2 clock in stead of 26 clock in the normal and 12 in the pipe-lining to increase its performance and speed it.
parallel AES encryption system
4792486
i modified the normal AES that uses 26 clock to the pipelining design that use just 12 clock and then i designed the parallel that use 2 clock.
pipelining AES encryption system
i modified the normal AES that uses 26 clock to the pipelining design that use just 12 clock and then i designed the parallel that use 2 clock.
pipelining AES encryption system
4792483
Normal AES encryption system that uses 26 clock to output results,i have modified this design in the pipe-lining design that uses 12 clock and then i modified the design again to use just 2 clock in the parallel design.
Normal AES encryption system
Normal AES encryption system that uses 26 clock to output results,i have modified this design in the pipe-lining design that uses 12 clock and then i modified the design again to use just 2 clock in the parallel design.
Normal AES encryption system
4091670
Designing UAV Using VHDL
Designing unmaned vehicle using FPGA
4091669
Designing UART Protocol
UART Protocol

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Kontakte Mohammed M. angående jobben din

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Engineering
Matlab and Mathematica
Verilog / VHDL
Microcontroller
Electrical Engineering

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Verilog / VHDL
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