Freelancer logo How It Works Bla gjennom jobber
Logg inn Registrer deg
Legg ut et prosjekt
Profilbilde
Du følger nå
Feil med følging av bruker.
Denne brukeren tillater ikke brukere å følge dem.
Du følger allerede denne brukeren.
Medlemskapsplanen din tillater bare 0 følginger. Oppgrader her.
Sluttet å følge
Kunne ikke slutte å følge bruker.
Du har vellykket anbefalt
Kunne ikke anbefale bruker.
Noe gikk galt. Oppdater siden og prøv igjen.
Vellykket bekreftelse av e-post.
Brukeravatar
$35 USD / time
EGYPTs flagg
beni suef, egypt
$35 USD / time
Det er for øyeblikket 9:53 a.m. her
Ble med mai 11, 2020
0 Anbefalinger

Moaz Khaled Feriz K.

@moaazkh96

verified.svg
 5,0 (73 omtaler)
5,8
5,8
93%
93%
$35 USD / time
EGYPTs flagg
beni suef, egypt
$35 USD / time
99 %
Jobber fullført
83 %
Innenfor budsjett
95 %
I tide
21 %
Gjenansettelsesrate

Digital Design Engineer. (FPGA, ASIC)

I am a full-time digital design engineer, I have a broad knowledge of digital design in ASIC and FPGA using both VHDL and Verilog. Interested in VLSI careers in both front-end (RTL) and back-end (syn, pnr....). I started my career on freelancing platforms 2.5 years ago, - Helping researchers and industry people to develop their digital designs, implement their papers. - Solving code problems. - Optimizing designs for speed, area and power. Through these projects I have improved my technical skills, applied my knowledge and grown my network with people around the globe. I have customers in USA, EU, China, India, Pakistan ... and many other countries, all of them were happy with their work done and so would you :) I am using the following tools and languages; FPGA : Vivado, ISE, and Quartus. ASIC : VCS, DVE, DC and spyglass. HDL : Verilog, System Verilog, VHDL. Scripting : Perl, tcsh, csh, tcl.
Freelancer Verilog / VHDL Designers Egypt
Se alle Verilog / VHDL Designers i Egypt

Kontakte Moaz Khaled Feriz K. angående jobben din

Logg inn for å diskutere eventuelle detaljer over chat.

Portefølje

6639217
I have designed a multiplier using only one adder in logsim program with a full report for submission.
design FSM multiplier
I have designed a multiplier using only one adder in logsim program with a full report for submission.
design FSM multiplier
I have designed a multiplier using only one adder in logsim program with a full report for submission.
design FSM multiplier
I have designed a multiplier using only one adder in logsim program with a full report for submission.
design FSM multiplier
6605692
designing and simulating both CMOs and NMOS inverters using Hspice providing a professional report for submission
CMOS design by Hspice
designing and simulating both CMOs and NMOS inverters using Hspice providing a professional report for submission
CMOS design by Hspice
designing and simulating both CMOs and NMOS inverters using Hspice providing a professional report for submission
CMOS design by Hspice
6584148
Verilog code design
a digital class assignment to make a verilog code of subtractor in behavioural modelling and test bench. I deliver it in few hours with full report ready to upload.
Verilog code design
a digital class assignment to make a verilog code of subtractor in behavioural modelling and test bench. I deliver it in few hours with full report ready to upload.
Verilog code design
6576510
a project of generation a Gray code on model sim by system Virloge then deploy it on FPGA.
Gray code display
6516140
A CS course project.
car number plate detection
6515736
1 Kbit SRAM layout using cadence, with clear DEC, LVS, PEX checks.
Cadence layout
6639217
I have designed a multiplier using only one adder in logsim program with a full report for submission.
design FSM multiplier
I have designed a multiplier using only one adder in logsim program with a full report for submission.
design FSM multiplier
I have designed a multiplier using only one adder in logsim program with a full report for submission.
design FSM multiplier
I have designed a multiplier using only one adder in logsim program with a full report for submission.
design FSM multiplier
6605692
designing and simulating both CMOs and NMOS inverters using Hspice providing a professional report for submission
CMOS design by Hspice
designing and simulating both CMOs and NMOS inverters using Hspice providing a professional report for submission
CMOS design by Hspice
designing and simulating both CMOs and NMOS inverters using Hspice providing a professional report for submission
CMOS design by Hspice
6584148
Verilog code design
a digital class assignment to make a verilog code of subtractor in behavioural modelling and test bench. I deliver it in few hours with full report ready to upload.
Verilog code design
a digital class assignment to make a verilog code of subtractor in behavioural modelling and test bench. I deliver it in few hours with full report ready to upload.
Verilog code design
6576510
a project of generation a Gray code on model sim by system Virloge then deploy it on FPGA.
Gray code display
6516140
A CS course project.
car number plate detection
6515736
1 Kbit SRAM layout using cadence, with clear DEC, LVS, PEX checks.
Cadence layout

Anmeldelser

Endringer lagret
Viser 1 - 5 av totalt 50+ omtaler
 Filtrer anmeldelser etter:
5,0
$2 000,00 USD
fpga video processing pipeline. -- 2
Good and professional delivery. Excellent communication
Electronics
Verilog / VHDL
FPGA
Brukeravatar
s flagg Felix L.
@felixlaz
•
10 måneder siden
5,0
₹5 000,00 INR
Verilog implementation of adam method
Moaz Khaled Feriz K is very dedicated towards work and shown results on time. I am happy and very much satisfied with his work.
Verilog / VHDL
FPGA
ASIC
Altera Quartus
+1 flere
J
s flagg Jillela M.
@jillelamahesh111
•
11 måneder siden
5,0
₹4 500,00 INR
Implementation of Gradient Descent Optimization Algorithms on FPGA in Verilog language which is synthesizable.
I love working with Moaz Khaled Feriz and he is very dedicated towards the project, he is the best freelancer which I have seen so far
Verilog / VHDL
FPGA
ASIC
Altera Quartus
+1 flere
J
s flagg Jillela M.
@jillelamahesh111
•
ett år siden
4,8
$473,01 USD
Debugging VHDL code for Nios Processor
He Know the subject very well [29 December, 2022] Knows subject very well [29 December, 2022] Knows subject very well [29 December, 2022] Knows subject very well [29 December, 2022] Knows subject very well
Verilog / VHDL
FPGA
ASIC
Altera Quartus
+1 flere
W
s flagg Kondi Wilfried K.
@Wkou23
•
ett år siden
5,0
$250,63 USD
MIPS Processor
He was awesome to work with. [26 December, 2022] Awesome work
Verilog / VHDL
FPGA
ASIC
Altera Quartus
+1 flere
M
s flagg Murjan U.
@murjanrahman
•
ett år siden

Erfaring

digital design engineer

freelancer .com
mai 2020 - Nå
I am helping researchers and post-grade students to implements their design as RTL with VHDL, Verilog and SystemVerilog for both FPGA and ASIC. I am using Vivado, ISE, Quartus and Modelsim. also I have experience in ASIC EDA tools like DC, ICC, ICC2 and PrimeTime.

Utdanning

Bachlore degree in nano-electronincs

Zewail City of Science and Technology, Egypt 2016 - 2021
(5 år)

Kontakte Moaz Khaled Feriz K. angående jobben din

Logg inn for å diskutere eventuelle detaljer over chat.

Verifiseringer

Foretrukket frilanser
Identitet verifisert
Betalingsverifisert
Telefonverifisert
E-postadresse verifisert
Koblet til Facebook

Sertifiseringer

preferredfreelancer-1.png Preferred Freelancer Program SLA 1 87%
us_eng_1.png US English 1 85%

Toppferdigheter

Verilog / VHDL 67
FPGA 55
ASIC 22
Altera Quartus 22
Digital ASIC Coding 21

Bla i lignende frilansere

Verilog / VHDL Designers in Egypt
Verilog / VHDL Designers
Field-Programmable Gate Array Experts
ASIC Engineers

Bla i lignende utstillinger

Verilog / VHDL
FPGA
ASIC
Altera Quartus
Forrige bruker Neste bruker
Invitasjonen ble sendt!
Takk! Vi har sendt deg en lenke for at du skal kunne kreve din gratis kreditt.
Noe gikk galt. Vær så snill, prøv på nytt.
Freelancer logo Norway / Norsk-Bokmål Hjelp og støtte Frilanser KategorierProsjekterKonkurranserFrilansereEnterprise MedlemskapForetrukken Frilanser-program ProsjektledelseLokale jobberPhoto AnywhereProsjektutstillingAPI for utviklereBli verifisertSkrivebordsapplikasjon Om Om ossHvordan det fungererSikkerhetInvestorSidekartHistorierI nyheteneTeamPremierPressemeldingerKarrierer Vilkår PersonvernBrukervilkårRetningslinjer for opphavsrettEtiske retningslinjerAvgifter og gebyrerPartnereEscrow.comLoadshiftWarrior Forum Apper Apple App Store logoGoogle Play logo
Kopiering til utklippstavlen mislyktes. Prøv igjen etter å ha justert tillatelsene dine.
Kopiert til utklippstavlen.
Registrerte brukere Publiserte jobber
Freelancer ® is a registered Trademark of Freelancer Technology Pty Limited (ACN 142 189 759)
Copyright © 2024 Freelancer Technology Pty Limited (ACN 142 189 759)
Forhåndsvisning innlasting
Tillatelse gitt for geolokalisering.
Påloggingsøkten din er utløpt og du har blitt logget ut. Logg på igjen.