I am a full-time digital design engineer,
I have a broad knowledge of digital design in ASIC and FPGA using both VHDL and Verilog.
Interested in VLSI careers in both front-end (RTL) and back-end (syn, pnr....).
I started my career on freelancing platforms 2.5 years ago,
- Helping researchers and industry people to develop their digital designs, implement their papers.
- Solving code problems.
- Optimizing designs for speed, area and power.
Through these projects I have improved my technical skills, applied my knowledge and grown my network with people around the globe.
I have customers in USA, EU, China, India, Pakistan ... and many other countries, all of them were happy with their work done and so would you :)
I am using the following tools and languages;
FPGA : Vivado, ISE, and Quartus.
ASIC : VCS, DVE, DC and spyglass.
HDL : Verilog, System Verilog, VHDL.
Scripting : Perl, tcsh, csh, tcl.