need to implement an ieee paper using verilog or vhdl. -- 2

Hello! I am an experienced Engineer and have been helping out many on this platform. It would be great if I could help you out. Thank you! Verilog and Digital Design - 4+ years

A proposal has not yet been provided

A proposal has not yet been provided

I had implemented one thesis and a paper before using verilog so, it is easy to extract the specs and implement any block diagram. Relevant Skills and Experience Implementing FFT/IFFT block for NB-IOT, I2C, UART and I2S protocols. Also, working on MIPS processor. Debugging in dot product RTL using NIOS II.

I am a senior year PhD Scholar at Shanghai Jiao Tong University, Shangahi China. My research is all about Reconfigurable Computing /Fast Arithmetic Circuits / Efficient Neural Network Accelerator Design, as you know its all connected with Verilog HDL. I have been working with Verilog HDL fro more tahn 5 years. I am pretty comfortable not only with writing Verilog HDL Code for simple to very complex systems such as DSP systems/ Embedded Control Systems and currently i am, developing Neural Network Accelerator Design which will be available on my github very soon. I have also written Custom IP Core packaging in to industry standard interfaces such as Xilinx AXI- Stream, AXI-Lite and AXI4 interfaces. In conclusion, i can code your design in Verilog RTL providing functional simulation as well as synthesis on a device (FPGA, SoC or mixed FPGA-SOC solution.

I have 10 years of experience in design and verification using Verilog on FPGA. Please message me. Thank you

I am 5 years experience in Digital ASIC/FPGA design with VHDL/Verilog and Systemverilog Either 10000 or adding me to the paper :)

A proposal has not yet been provided

I have 5 years of professional experience in implementing VHDL or verilig codes from IEEE paper. I can give you guarantee that the required algorithm will be implemented. The milestones will be as follows: 1. Read paper, understand and discuss the specifications. 2. After finalizing the specifications I will submit a block diagram. 3. Then I will finish the code and make it run 4. Then submit final deliverables