Design Verification

$30-250 USD

Stengt

Lagt ut

over 4 år siden

$30-250 USD

Betalt ved levering

PCle, ethernet , UVM, System Verilog

FPGA

Verilog / VHDL

Prosjekt-ID: 22356504

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2 forslag

Eksternt prosjekt

Aktiv 4 år siden

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2 frilansere byr i gjennomsnitt $131 USD for denne jobben

@hungfreelancer

I have 10 years of experience in design and verification using Verilog and SystemVerilog, VMM. Please message me. Best regards.

$111 USD om 5 dager

5,0

(8 omtaler)

4,2

@abubakarayyub01

Hello Dear Concern, We are a team of professional members of Electrical, Electronics, Mechanical, Civil, Chemical, Energy, Industrial Engineering. We are also expert in following softwares: MATLAB, Simulink, VHDL, PADS, PORTEL,Proteus, Cadence ,Solidworks PCB, ANSYS, ABACUS, AUTOCAD, DipTrace, Kidcad, MATLAB, SPSS, PRO/E, CATIA V5, Stud pro, Homer Pro, We are trusted people and will never break you trust. We will deliver your work with in your defined timeline. I assure you that your work will be error free and 100% professional with high quality. We will never waste your time and money. We will try over best to make you proud. Please consider me for this job. Thank you in advance. Regards,

$150 USD om 3 dager