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adc data decoding module

$30-250 USD

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Lagt ut over 5 år siden

$30-250 USD

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Design adc data decoding module. (vivado 2018.2) Input: FCLK,DCLK,DATA_0~DATA_15.(all input signals are LVDS) Output: CLKOUT, DOUT_0 [15:0] ~ DOUT_31 [15:0]. One data path contains two adc signals. The two adc signals are distinguished by FCLK level. I need to decode the adc data into 16-bit wide data and output a total of 32 channels of adc data. The input waveform is shown in the figure. The difference is that the data is D0~D15.
Prosjekt-ID: 18323398

Om prosjektet

8 forslag
Eksternt prosjekt
Aktiv 5 år siden

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8 frilansere byr i gjennomsnitt $257 USD for denne jobben
Brukeravatar
Dear sir I have more than 10 years experience in digital design using FPGA, i saw the attachment and i can do the required design perfectly Best regards
$200 USD om 1 dag
4,9 (431 omtaler)
7,8
7,8
Brukeravatar
Dear Sir. I am very interested in your project and I would be happy to work on it. I can make the design of the adc data decoding module in VHDL. I am a Senior Electronic Engineer with experience in the design / development of embedded systems implemented with DSP, FPGA and Microcontrollers. In my 6+ years of experience in the Aerospace and IoT industries, I worked in electronic/circuit design, PCB layout, embedded C programming and digital design. In my experience in the aerospace area, I worked in high-speed designs on FPGAs using VHDL. I have the skill to solve problems, the rapid understanding of what is required, seriousness and responsibility to carry out the work in the best way. I am new to the freelance platform, but I am sure that I am the professional who can do this job. You can trust that I will give my best to deliver a work that exceeds your expectations. Thanks for your consideration Best regards
$220 USD om 3 dager
5,0 (6 omtaler)
6,2
6,2
Brukeravatar
Hi, I am Quan, I have 5+ years experiences in FPGA and ADC/DAC interface. This is Double Data Rate LVDS. I have done several projects like that. I will finish your project on time.
$200 USD om 3 dager
4,8 (16 omtaler)
4,7
4,7
Brukeravatar
I am an experienced digital design engineer with VHDL and Xilinx knowledge. Regarding this project, I have previously worked interfacing LVDS signals in video processing. As part of this project I'll design the interface circuits against the provided spec in VHDL. Which FPGA part are you targeting? Drop a line over chat if you have any questions, kind regards
$230 USD om 10 dager
5,0 (6 omtaler)
4,2
4,2
Brukeravatar
I have pretty good experience with FPGA & ASIC design. I have read teh details of your project. I can get you the job done.
$222 USD om 7 dager
4,5 (7 omtaler)
3,6
3,6
Brukeravatar
I have completed many projects in vivado. I have background in digital and signal processing domain. Please check the profile.
$266 USD om 3 dager
5,0 (2 omtaler)
2,8
2,8
Brukeravatar
Hello there i am krishna from Digitronix , We have worked on multiple projects on ADC Design and decoding. Our first project was the Sigma Delta ADC Design and another is interfacing the ADC and DAC for adding delay and distortion features on the original signal with FFT/IFFT and filter's. Let me know your interest!
$160 USD om 7 dager
4,8 (1 omtale)
1,4
1,4
Brukeravatar
I will definitely complete your project with in your deadline as per your requirement.I am experienced in such kind of projects.
$555 USD om 1 dag
0,0 (0 omtaler)
0,0
0,0

Om klienten

CHINAs flagg
Shenzhen, China
0,0
0
Medlem siden des. 3, 2018

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