VHDL FPGA Project

This Project focuses on the use of VHDL language to describe a simple design and to verify its correct operation through test benches and simulations. The implementation on a specific FPGA has to allow also to obtain additional information of consumption, frequency of operation, etc. In short, it is a matter of following a design process as close to the real as possible, but in a controlled environment with a simple design. Requirements • To know the general characteristics and tools involved in the design process of a specific application integrated circuit (ASIC), specifically a FPGA. • Know how to implement logical functions in programmable logical devices using description languages of Hardware, in particular, VHDL. • Know how to design on FPGAs using specific techniques, and verifying the correct operation of the implementation of the result. FORMAT AND DATE OF DELIVERY • You have to deliver the solution to the project In a ZIP file, which contains the solution In PDF format using the template delivered in conjunction with this statement, as well as the Complete Designs File Exercises that require VHDL coding (using the tool from the Quartus, Project-> Archive Project). • The PDF memory has to include all the code in VHDL, both in the Di Teach as of the test benches used in the simulations as well as all the graphs obtained, along with the right comments. Think that if there is a problem to reproduce the results of your Di This will be the only thing left to defend your Work. • The delivery deadline is the 19 of December (At 24 Hours GMT + 1 – Spain timetable). DESCRIPTION OF PROJECT This Project is composed in 3 parts that can work more or less Independently: • Part 1: It is a matter of modifying the operation of a VHDL module that is already given to us to adapt it to our needs. To do it you will have to synthesize and check through a bank of Tests (test bench). • Part 2: It is a question of implementing in an FPGA, and subsequently verifying its operation by means of a test bench, a small design that uses the modified block in the preceding section. • Part 3: In this last part you want to work with advanced tools available in design environments that manufacturers of FPGAs within our reach: visualizers of the result of the synthesis process, ITools of temporal analysis and consumption. All the files needed are attached.