Modify LimeSDR FPGA

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The LimeSDR-USB allows to either transmit signals at once or schedule them. In all cases the samples must be passed from the host to the device at each call, which can take time due to the USB speed and latency.

We would like to be able to just tell the device to transmit a specific type of signal, either at once or at a specific timestamp, without passing the samples each time. The different signals to transmit could have been uploaded to the device previously (the LimeSDR-USB already allows to upload one, but its usage is limited) , or perhaps the device itself could generate them.

This would require modifying the FPGA, as well as some of the C APIs to either add or expand existing functions.

C-programmering Verilog / VHDL FPGA Radio Frequency Engineering Elektrisk ingeniørvitenskap

Prosjekt-ID: #30549099

Om prosjektet

8 bud Eksternt prosjekt Aktiv 2 år siden

8 frilansere byr i gjennomsnitt $2988 for denne jobben

IvanTolstenko

Hello, I'm glad to be here. I'm an expert in FPGA VHDL/Verilog and MATLAB/Simulink VHDL coder. I've rich experiences of FPGA applications in communications and DSPs such as GPS signal proccessing. I'm very interested i Mer

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FineIdeas

Modify LimeSDR FPGA Since 2012, almost from 8 years I am managing academic writing tasks successfully. I am working with my friends from different backgrounds, it means I can manage wide range of projects like; Engine Mer

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Alfons5

Hello!!! I would be glad of working with you. I have studied electronics for 21 years, so for sure I will be helpful. We should just chat and agree. Bye!!!!

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vpapayan

Hi, there. I am Valentine, senior developer. I've checked your post and I understood what you want. I'd like to dedicate to your project and build long-term relationship with you. Thanks for your attention. Valentine.

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