We are looking for freelancer to develop FPGA software alghorithm for Cryptonight V7 mining using Xilinx Virtex UltraScale+ FPGA VCU1525 card. Develop FPGA bitstream for mining Cryptonight v7 (CN7) algorithm on Xilinx Virtex UltraScale+ FPGA VCU1525 card + modify the miner software on PC to communicate with the FPGA. Miner software can communicate
We are looking for one freelancer to develop FPGA software for Cryptonight mining using Xilinx Virtex UltraScale+ FPGA VCU1525 card. You will have to program an FPGA card that I will provide, to work for crypto mining. Is necessary also customize mining software that works under Windows to by able to works with the FPGA. Software must have to be
Hi, there I am looking for an experienced FPGA developer that can implement HASH algorithm on FPGA. We can discuss in details via chatting. Please contact me! I am waiting for someone now. Welp,
1. FIR design and simultion in Matlab. 2. Implement in FPGA(Xilinx Virtex-6 LX240T) and inter-connect with other logic blocks. 3. define registers for FIR filter and gain setting such that user can download filter co-efficients and gain settings through software to FPGA.
Could somebody help me with some algorithms? Scenario: You have been invited to design and develop a ticketing system for ICT help desk at Virtex College. The current ICT help desk works based on FIFO strategy. That means the first request received by help desk is the first request processed by ICT’s technicians. This system has couple of critical issues
...implement algorithms as a program using C# visula basic. Scenario:You have been invited to design and develop a ticketing system for ICT help desk at Virtex College. The current ICT help desk works based on FIFO strategy. That means the first request received by help desk is the first request processed by ICT’s technicians. This system has couple of critical
...ready for interview” in your bid so that I should know that you have read my project description, else REJECTED! I need presentations (ppt) on the following: 1. Xilinx Virtex-7 FPGA 2. System Verilog 3. PIC 4. Network on Chip (NoC) 5. AVR Architecture Furthermore, I need ppt converted to pdf of 1. RISC 2. CISC 3. Power PC
The implementation of the Xilinx free Aurora core to transfer data in one direction only between two Virtex-5 (xc5vlx110t) chips mounted on two ML505 prototyping boards, and running a test with an image stored onboard. Minimum speed acceptable 1.5Gbps. The project is more than 50% done, need to finalize it and test.
single precision floating point multiplier using booths algo implementable on virtex 7 fpga xilinxs ...need it urgently
Hardware: Xilinx Virtex 7 FPGA - XC7VX415T Objective: - Read Datagrams(IP Packets) arriving on port on FPGA. - Record Source IP, Destination IP and Counter Number in Data-part of Packet. - Capture the information and save locally or send it to remote server as syslog. - Discard rest of the the IP packet. Example: Look at the attached PDF
Write a pcie driver for a xilinx virtex 7 fpga. DMA performance is the most important. Must have own fpga to test with. Expect delivery of a fpga core and driver with C# wrapper. Starting with 3rd party tool such as jungo is ok. Must interface managed C# code.
There will be 3 or 4 users whose speech will be captured using microphone array and needs to sampled and stored in fpga. The algorithm like MUSIC...sampled and stored in fpga. The algorithm like MUSIC, Root-MUSIC, ESPRIT, Bartlett etc then estimates the stored sampled and gives the direction of arrival angle to LCD on Xilinx Virtex 4 development kit.
Our team is developing satellite communication systems with Xilinx FPGA. We are expecting FPGA designers that skilled with Xilinx Virtex-5. The module must operate in 350MHz. Please contact me who are interesting.
Hardware: Network device with inbuilt and programmable Xilinx Virtex 7 or Altera Stratix V 320 Gbps FPGA. Requirement: Parse the traffic passing though the network device for certain information and log it locally. Which will be analyzed by security engine (Not in scope of this project) Detailed requirement: Step 1: Configure FPGA to read
I want to implement 9 2D image filtering using convolution operation on Cortex/Virtex I need to burn it and using perform cosimulation in matlab system generation exactly as described in attatched paper. The performance graphs should be generated as shown in paper. I need simultaneous operations of all nine mask operations.
...project is to initialize and control the Virtex and DAC on the VC707 through Vivado and LabVIEW. It will need to be demonstrated at our end with a VPN connection that I will provide. The designer can work remotely on the development computer here as required. The controls will be: 1. INITIALIZE Virtex and DAC 2. START/STOP 3. FREQUENCY 4. AMPLITUDE